DK-DEV-5SGXEA7N【PDF 262/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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9-2

User Mode Error Detection

SV51011

2014.01.10

User Mode Error Detection

In user mode, the contents of the configured CRAM bits may be affected by soft errors. These soft errors,

which are caused by an ionizing particle, are not common in Altera devices. However, high-reliability

applications that require the device to operate error-free may require that your designs account for these

errors.

You can enable the error detection circuitry to detect soft errors. Each data frame stored in the CRAM

contains a 32-bit precomputed CRC value. When this feature is enabled, the error detection circuitry

continuously computes a 32-bit CRC value for each frame in the CRAM and compares the CRC value against

the precomputed value.

? If the CRC values match, the 32-bit CRC signature in the syndrome register is set to zero to indicate that

no error is detected.

? Otherwise, the resulting 32-bit CRC signature in the syndrome register is non-zero to indicate a CRC

error. The CRC_ERROR pin is pulled high, and the error type and location are identified.

Within a frame, the error detection circuitry can detect all single-, double-, triple-, quadruple-, and quintuple-

bit errors. When a single-bit or double-adjacent error is detected, the error detection circuitry reports the

bit location and determines the error type for single-bit and double-adjacent errors. The probability of other

error patterns is very low and the reporting of bit location is not guaranteed. The probability of more than

five CRAM bits being flipped by soft errors is very low. In general, the probability of detection for all error

patterns is 99.9999%. The process of error detection continues until the device is reset by setting the nCONFIG

signal low.

Internal Scrubbing

Internal scrubbing is the ability to internally correct soft errors in user mode. This feature corrects single-

bit and double-adjacent errors detected in each data frame without the need to reconfigure the device.

Figure 9-1: Block Diagram

Error Detection

State Machine

Data Registers, CRC

32-Bit CRC

Calculation and Error

Internal Scrubbing

Registers, and CRAM

Array

Search Engine

Specifications

This section lists the EMR update interval, error detection frequencies, and CRC calculation time for error

detection in user mode.

Minimum EMR Update Interval

The interval between each update of the error message register depends on the device and the frequency of

the error detection clock. Using a lower clock frequency increases the interval time, hence increasing the

time required to recover from a single event upset (SEU).

Altera Corporation

SEU Mitigation for Stratix V Devices

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